The semiconductor industry currently uses different types of semiconductor-based imagers, including charge coupled devices (CCD) and CMOS imager devices. Because of the inherent limitations in CCD technology, CMOS imagers have been increasingly used as low-cost imaging devices. A fully compatible CMOS sensor technology enabling a higher level of integration of an image array with associated processing circuits is beneficial for many digital applications.
A CMOS image sensor circuit includes a focal plane array of pixel cells, each one of the cells including a photoconversion device, for example, a photogate, photoconductor, or a photodiode for accumulating photogenerated charge in a doped portion of the substrate. A readout circuit is connected to each pixel cell and includes at least an output transistor, which receives photogenerated charges, typically from a doped floating diffusion region, and produces an output signal which is periodically read-out through a row select access transistor. The imager may optionally include a transistor for transferring charge from the photoconversion device to the floating diffusion region or the floating diffusion region may be directly connected to or part of the photoconversion device. A transistor is also typically provided for resetting the floating diffusion region to a predetermined charge level before it receives the photoconverted charges.
In a conventional CMOS imager, the active elements of a pixel cell perform the necessary functions of: (1) photon to charge conversion; (2) accumulation of image charge; (3) transfer of charge to the floating diffusion node; (4) resetting the floating diffusion node to a known state before the transfer of charge to it; (5) selection of a pixel for readout; and (6) output and amplification of signals representing the reset state and a pixel charge signal. Photo-charge may be amplified when it moves from the initial charge accumulation region to the floating diffusion node through a transfer transistor. The charge at the floating diffusion node is converted to a pixel output voltage by the source follower output transistor.
A known three-transistor (3T) CMOS active pixel sensor (APS) design used in many applications contains a photodiode for producing charges which are stored at a diffusion region, a reset transistor for resetting the diffusion region charge, a source follower transistor having a gate connected to the diffusion region for producing an output signal, and a row select transistor for selectively connecting the source follower transistor to a column line of a pixel array. In a four-transistor (4T) CMOS configuration, a transfer transistor is employed to gate charges from the photodiode to the diffusion region.
A schematic top view of a semiconductor wafer fragment of an exemplary CMOS sensor pixel four-transistor (4T) cell 10 is illustrated in FIG. 1. As it will be described below, the CMOS sensor pixel cell 10 includes a photogenerated charge collection region 21, in a doped portion of the substrate, for collecting charges generated by light incident on the pixel cell 10. This region 21 is formed as a pinned photodiode 11 (FIG. 2). The photodiode 11 is termed “pinned” because the potential in the photodiode 11 is pinned to a constant value when the photodiode 11 is fully depleted. It should be understood, however, that the CMOS sensor pixel cell 10 may include a photogate or other photon to charge converting device, in lieu of a pinned photodiode 11, as the initial collection region 21 for photogenerated charge.
The CMOS image sensor 10 of FIG. 1 has a transfer transistor with gate 30 for transferring photoelectric charges from the charge collection region 21 to a sensing node 25, typically a floating diffusion region. The sensing node 25 is electrically connected to the gate 50 of an output source follower transistor. The source follower transistor provides an output signal to a row select access transistor having gate 60 for selectively gating the output signal to terminal 32′. A reset transistor having gate 40 resets the sensing node 25 to a predetermined voltage before charge is transferred thereto from the charge collection region 21. The CMOS image sensor 10 of FIG. 1 also includes a n-type region 26 further illustrated in FIG. 2.
A cross-sectional view of the exemplary CMOS image sensor 10 of FIG. 1, taken along line 2–2′ is illustrated in FIG. 2.
The exemplary pixel 10 of FIG. 2 employs pinned photodiode 11 having charge collection region 21 for converting photons to charge. The pinned photodiode 11 has a photosensitive p-n-p junction region comprising a p-type surface layer 24, a n-type region 26, within a p-type substrate 20. Impurity doped source/drain regions 22 (FIG. 1) having n-type conductivity, are provided on either side of the transistor gates 40, 50 and 60. The floating diffusion region, e.g., sensing node 25, adjacent to the transfer gate 30 is also preferably n-type. In addition, p-wells 94 are provided on either side of the pinned photodiode 11 in the p-type substrate 20.
Generally, in CMOS image sensors such as CMOS image sensor cell 10 of FIGS. 1–2, incident light causes electrons to accumulate in n-type region 26. A maximum output signal, which is produced by the source follower transistor having gate 50, is proportional to the number of electrons extracted from the region 26. The maximum output signal increases with increased electron capacitance or acceptability of the region 26 to acquire electrons. The electron capacity of pinned photodiodes typically depends on, among other things, the dopants implanted into the photodiode active layer 21. In particular, regions 24, 26 dominate the pinned photodiode's 11 capacitance. Accordingly, increasing the pinned photodiode's 11 capacitance is useful to allow capture of greater levels of photoconverted charges.
Conventionally, trench isolation regions 15 formed in a p-well active layer 94 and adjacent to the charge collection region 21, are used to isolate the pixels. The trench isolation regions 15 are typically formed using a conventional STI process or by using a Local Oxidation of Silicon (LOCOS) process. A translucent or transparent insulating layer 55 formed over the CMOS image sensor 10 is also illustrated in FIG. 2. Conventional processing methods are used to form, for example, contacts 32 (FIG. 1) in the insulating layer 55 to provide an electrical connection to the source/drain regions 22, the floating diffusion region 25, and other wiring to connect to gates and other connections in the CMOS image sensor 10.
Trench isolation regions 15 are typically formed by etching trenches into the substrate 20 to provide a physical barrier between adjacent pixels to isolate pixels optically and electrically from one another. The trenches 15 are etched by employing a dry anisotropic or other suitable etching process, and are then filled with a dielectric such as a chemical vapor deposited (CVD) silicon dioxide (SiO2). The filled trenches 15 are then planarized so that the dielectric remains only in the trenches and their top surface remains level with that of the silicon substrate 20.
A common problem associated with the formation of the above-described trench isolation regions 15 is that when ions are implanted in the substrate close to the bottom 17 and sidewalls 16 (FIG. 2) of the trench, current leakage can occur at the junction between the active device regions and the trench. In addition, the dominant crystallographic planes along the bottom 17 and sidewalls 16 of the trench isolation regions 15 have a higher silicon density than the adjacent silicon substrate and, therefore, create a high density of trap sites along the trench bottom 17 and sidewalls 16. These trap sites are normally uncharged but become charged when electrons and holes become trapped in the trap sites. As a result of these trap sites formed along the bottom 17 and sidewalls 16 of the trench isolation regions 15, current generation near and along the trench bottom 17 and sidewalls 16 can be significant. Current generated from trap sites inside or near the photodiode depletion region causes undesired dark current.
Further, for proper operation of the pinned photodiode 11, the p-type surface implant region 24 must be continuously connected using p-type dopants to the p-type substrate 20. FIG. 2 illustrates this as link region 96. Accordingly, a continuous p-type region from p-type surface layer 24 through link region 96 to p-well 94 and on to p-type substrate 20 must be established for the pinned photodiode 11 to work properly. In situations where this does not occur, the surface p-type region 24 becomes isolated from the p-type substrate 20 and results in the p-type surface region 24 to float rather than being pinned. This results in a dramatic loss in the pinned photodiode's 11 capacitance and therefore, decreased image sensor performance.
One solution is to make the p-well region 94 wider so that it overlaps with the surface p-type region 24. However, this requires that the n-region 26 to become smaller. Thereby, pulling the n-region 26 farther away from the p-well region 94. If the n-region 26 is not moved farther from the p-well region 94, the dark current generated by the image sensor is increased.
Reducing dark current in the photodiode is important in CMOS image sensor fabrication. Dark current is generally attributed to leakage in the charge collection region 21 of the pinned photodiode 11, which is strongly dependent on the doping implantation conditions of the CMOS image sensor. In addition and as explained above, defects and trap sites inside or near the photodiode depletion region strongly influence the magnitude of dark current generated. In sum, dark current is a result of current generated from trap sites inside or near the photodiode depletion region; band-to-band tunneling induced carrier generation as a result of high fields in the depletion region; junction leakage coming from the lateral sidewall of the photodiode; and leakage from isolation corners, for example, stress induced and trap assisted tunneling.
CMOS imagers also typically suffer from poor signal to noise ratios and poor dynamic range as a result of the inability to fully collect and store the electric charge collected in the region 26. Since the size of the pixel electrical signal is very small due to the collection of electrons in the photo array, the signal to noise ratio and dynamic range of the pixel should be as high as possible.
One previous method employed to address dark current is illustrated in FIG. 3A. A pinned photodiode 11 was formed to a predetermined distance away from the active area of the pixel cell 10. However, if the pinned photodiode 11 was less than 0.30μ away from the active area, then the pinned photodiode's 11 dark current has been observed to increase. In particular, the n-region 26 is far removed from the isolation region 15, e.g., greater than 0.30μ, illustrated in FIG. 3B, which is a schematic cross-sectional view of the pixel cell 10 of FIG. 3A taken along line 2–2′. Specifically, the pinned photodiode 11 of FIG. 3, exhibits reduced photodiode capacitance as a result of having a smaller effective charge collection region 21. The pixel cell 10 of FIGS. 3A–3B, however, does exhibit lower dark current at the trade-off of having reduced capacitance.
In another method employed to address dark current concerns, FIG. 4A illustrates that the pinned photodiode 11 was formed to overlap the active area of the pixel cell 10. In particular, the n-region 26 overlaps the isolation region 15 as FIG. 4B illustrates, which is a schematic cross-sectional view of the pixel cell 10 of FIG. 4A taken along line 2–2′. Nonetheless, this pixel design also increased the generation of dark current using a conventionally formed isolation region 15. Specifically, pixel cell 10 has a larger effective charge collection region 21 yielding greater capacitance. The pixel cell 10 of FIGS. 4A–4B, however, exhibits higher dark current at the trade-off of having increased capacitance.
What is required is a means to increase the n-photodiode collection region 26 without causing increased dark current and also achieving a p-type link 96 between the surface p-type region 24 through pwell 94 and to the p-type substrate 20.
There is needed, therefore, an improved active pixel photosensor for use in a CMOS imager that is resistant to dark current and has good photodiode capacitance. An improved isolation region that prevents current generation or current leakage and allows an increased pinned photodiode collection area to be formed closer to the trench isolation region is desired. A method of fabricating an active pixel photosensor exhibiting these characteristics is also needed.